US-TX-Dallas Mixed Signal Design Verification Engineer, 3127
US-NC-Raleigh Contract IC Layout/Mask Designer, 3129

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US-TX-Dallas Mixed-Signal Design Verification Engineer, 3127

4 month contract in Dallas,Texas area

Mixed-Signal Design Verification Engineer will execute the pre-silicon verification of mixed-signal IC products. Implement mixed-signal test-benches to apply stimulus and checks to verify DUT behavior. Utilize Verilog, Verilog-A, Verilog-AMS to stimulus and check mixed-signal circuits. Create SystemVerilog functional coverage models of mixed-signal circuits for voltages and currents, real numbers, integers, and traditional digital functional coverage. Work with complex mixed-signal semiconductor chip designs. Work with design and systems teams to close bugs as they arise. Review the digital and analog design to provide guidance on Design for Verification architecture and features during chip development. Evaluate system-level use-cases and re-create these in simulation, including communication with customers to convey results and understand these system cases.

Use Cadence Virtuoso, spectre spice simulation, Incisive and AMS simulators. Utilize RTL and Gates+SDF, including verifying chip-level timing between analog and digital circuits. Constrained-random stimulus and auto-checking verification environments, especially constrained random analog stimulus. Work in bug tracking and RTL code coverage. Create behavioral models of analog circuits and verifying closed-loop simulation with digital design and analog behavioral models.

- B.S. in Electrical Engineering and 5 years of experience in Analog Design, Digital Design, or equivalent experience.
- Verification planning, development of verification/test plans using system/block/sub-system specs/datasheet
- Scripting and automation using Unix/Linux shell, PERL, Python, C or other similar languages
- SystemVerilog, Verilog RTL, Verilog-AMS and Verilog-A
- Digital synthesis, timing closure, place-and-route, Gates+SDF simulation
- Analog circuit design, transient, DC, AC simulation and Monte Carlo analysis
- Cadence Virtuoso, Spectre circuit simulator, Incisive and AMS simulators
- Circuit layout, parasitic extraction
- IC chip design, assembly and tapeout lifecycle and flow
- Advanced verification tools and skills such as SystemVerilog, UVM, functional and code coverage, formal property checking, constrained-random stimulus, auto checking

LOCATION: Contract on-site for customer Dallas, Texas
Submit Resume

US-NC-Raleigh Contract IC Layout Mask Designer, 3129

3 month contract starting in April, 2017

Power IC Layout/verification utilizing Cadence Virtuoso and Assura/Calibre. Layout will include mostly analog techniques with some digital circuits and can include several of the following:
- Analog circuits such as amplifiers, ADC, DAC, oscillators.
- ESD structures and pad-ring assembly.
- Understanding of construction and purpose of guard ring structures.
- Familiar with Assura/Calibre verification.
- Circuitry for DC-DC converters.
- High-Current Pulse-Width-Modulation circuits.
- Circuits for LED Driver ICs.
- High-Voltage (over 20/30 volts) and low-voltage triple-well isolated MOS.
- High-current voltage regulators (LDOs).

- 5+ years Analog Layout Experience preferred
- TSMC experience
- Direct experience in Power IC layout using IC processes that include CMOS, Bipolar and DMOS devices.
- BCD process is a plus.
- Cadence layout environment. Assura/Calibre verification tools.

MISC: US Citizen or permanent resident.
Submit Resume


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